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ST8016 160 output lcd common/ segment driver ic datasheet note: sitronix technology corp. reserves the right to change the contents in this document without prior notice. this is not a final specification. some parameters are subject to change. version 2.0 2008/05/07
ST8016 ver 2.0 page 2/28 2008/05/07 1 features n number of lcd drive outputs: 160 n supply voltage for lcd drive: +15.0 to +30.0 v n supply voltage for the logic system: +2.5 to +5.5 v n low power consumption n low output impedance (segment mode) n shift clock frequency - 20 mhz (max.): v dd = +5.0 0.5 v - 12 mhz (max.): v dd = +3.0 to + 4.5 v - 8 mhz (max.): v dd = +2.5 to + 3.0 v n adopts a data bus system n 4-bit/8-bit parallel input modes are selectable with a mode (md) pin n automatic transfer function of an enable signal n automatic counting function which, in the chip selection mode, causes the internal clock to be stopped by automatically counting 160 bits of input data n line latch circuits are reset when /dispoff active (common mode) n shift clock frequency: 4 mhz (max.) n built-in 160-bit bi-directional shift register (divisible into 80 bits x 2) n available in a single mode (160-bit shift register) or in a dual mode (80-bit shift register x 2) - y 1 ->y 160 single mode - y 160 ->y 1 single mode - y 1 ->y 80 , y 81 ->y 160 dual mode - y 160 ->y 81 , y 80 ->y 1 dual mode the above 4 shift directions are pin-selectable n shift register circuits are reset when /dispoff active 2 description the ST8016 is a 160-output segment/common driver ic suitable for driving large/medium scale dot matrix lcd panels, and is used in personal computers/work stations. through the use of sst (super slim tcp) technology, it is ideal for substantially decreasing the size of the frame section of the lcd module. the ST8016 is good both as a segment driver and a common driver, and it can create a low power consuming, high-resolution lcd.
ST8016 ver 2.0 page 3/28 2008/05/07 3 pin connections package: 186-pin tcp (tape carrier package) 4 pin description (tcp) pin no. symbol i/o description 1 ~ 160 y 1 -y 160 o lcd drive output 161,186 v 0l , v 0r p power supply for lcd drive 162,185 v 12l , v 12r p power supply for lcd drive 163,184 v 43l , v 43r p power supply for lcd drive 165 l/r i display data shift direction selection 166 v dd p power supply for logic system (+2.5 to +5.5 v) 167 s/c i segment mode/common mode selection 168,180 eio 2 , eio 1 i/o input/output for chip selection at segment mode shift data input/output for shift register at common mode 169 ~ 175 di 0 -di 6 i display data input at segment mode 176 di 7 i display data input at segment mode/dual mode data input at common mode 177 xck i clock input for taking display data at segment mode 178 /dispoff i control input for output of non-select level 179 lp i latch pulse input for display data at segment mode/ shift clock input for shift register at common mode 181 fr i ac-converting signal input for lcd drive waveform 182 md i mode selection input 164,183 v ss p ground (0 v) p: power pin 1 160 161 186 y 1 y 158 y 159 y 160 y 3 y 2 v 0r v 0l eio 1 lp /dispoff xck di 0 eio 2 s/c v dd v 43l v 12l di 1 di 7 di 6 di 5 di 4 di 3 di 2 fr v ss v 43r v 12r l/r md 186 pin tcp c h i p s u r f a c e v ss
ST8016 ver 2.0 page 4/28 2008/05/07 5 block diagram 6 functional operations of each block block function active control in case of segment mode, controls the selection or non-selection of the chip. following an lp signal input, and after the chip sel ection signal is input, a selection signal is generated internally until 160 bits of data have been read in. once data input has been completed, a selection signal for cascade connection is output, and the chip is non-selected. in case of common mode, controls the input/output data of bi-directional pins. sp conversion & data control in case of segment mode, keeps input data which are 2 clocks of xck at 4-bit parallel input mode in latch circuit, or keeps input data which are 1 clock of xck at 8-bit parallel input mode in latch circuit; after that they are put on the internal data bus 8 bits at a time. data latch control in case of segment mode, selects the state of the data latch which reads in the data bus signals. the shift direction is controlled by the control logic. for every 16 bits of data read in, the selection signal shifts one bit based on the state of the control circuit. data latch in case of segment mode, latches the data on the data bus. the latch state of each lcd drive output pin is controlled by the control logic and the data latch control; 160 bits of data are read in 20 sets of 8 bits. line latch/ shift register in case of segment mode, all 160 bits which have been read into the data latch are simultaneously latched at the falling edge of the lp signal, and are output to the level shifter block. in case of common mode, shifts data from the data input pin at the falling edge of the lp signal. level shifter the logic voltage signal is level-shifted to the lcd drive voltage level, and is output to the driver block. 4-level driver drives the lcd drive output pins from the line latch/shift register data, and selects one of 4 levels (v0, v12, v43 or vss) based on the s/c, fr and /dispoff signals. control logic controls the operation of each block. in case of segment mode, when an lp signal has been input, all blocks are reset and the control logic waits for the selection signal output from the active control block. once the selection signal has been output, operation of the data latch and data transmission is controlled, 160 bits of data are read in, and the chip is non-selected. in case of common mode, controls the direction of data shift. 160-bit 4-level driver 160-bit level shifter 160-bit line latch/shift register data latch control sp conversion & data control (4 to 8 or 8 to 8) control logic active control level shifter 8 bit data latch di0di1di2di3di4di5di6di7v dd v ss v 43l v 12l v 0l y 160 y 159 y 2 y 1 v 43r v 12r v 0r fr dispoff eio 1 eio 2 lp xck l/r md s/c 8 1616 16 160 160
ST8016 ver 2.0 page 5/28 2008/05/07 7 input/ output circuits figure 7-1 input circuit (1) figure 7-2 input circuit (2) figure 7-3 input circuit (3) i v dd to internal circuit vss (0v) applicable pins l/r , s/c , di 6 ~di 0 , dispoff , lp , fr , md i v dd to internal circuit applicable pins di 7 , xck vss (0v) vss (0v) control signal i v dd to internal circuit applicable pins test 1 , test 2 vss (0v) vss (0v) v dd
ST8016 ver 2.0 page 6/28 2008/05/07 figure 7-4 input/output circuit figure 7-5 lcd drive output circuit v dd i/o to internal circuit vss (0v) vss (0v) control signal vss (0v) v dd output signal control signal application pins eio 1 , eio 2 o vss (0v) v 0 control signal 1 control signal 3 control signal 2 control signal 4 v 0 v 12 v 43 v 5 v ss (0v) application pins y 1 ~y 160
ST8016 ver 2.0 page 7/28 2008/05/07 8 functional description 8.1 pin functions (segment mode) symbol function v dd logic system power supply pin, connected to +2.5 to +5.5 v. v ss ground pin, connected to 0 v. v 0l , v 0r v 12l , v 12r v 43l , v 43r bias power supply pins for lcd drive voltage ? normally use the bias voltages set by a resistor divider ? ensure that voltages are set such that v ss < v 43 < v 12 < v 0 . ? v il and v ir (i = 0,12, 43) must connect to an external power supply, and supply regular voltage which is assigned by specification for each power pin di 7 -di 0 input pins for display data ? in 4-bit parallel input mode, input data into the 4 pins, di 3 -di 0 . connect di 7 -di 4 to v ss or v dd . ? in 8-bit parallel input mode, input data into the 8 pins, di 7 -dl 0 . ? refer to "relationship between the display data and lcd drive output pins" in functional operations. xck clock input pin for taking display data * data is read at the falling edge of the clock pulse. lp latch pulse input pin for display data ? data is latched at the falling edge of the clock pulse. l/r input pin for selecting the reading direction of display data ? when set to v ss level "l", data is read sequentially from y 160 to y 1 . ? when set to v dd level "h", data is read sequentially from y 1 to y 160 . ? refer to "relationship between the display data and lcd drive output pins" in functional operations. /dispoff control input pin for output of non-select level ? the input signal is level-shifted from logic voltage level to lcd drive voltage level, and controls the lcd drive circuit. ? when set to v ss level "l", the lcd drive output pins (y 1 -y 160 ) are set to level vss. ? when set to "l", the contents of the line latch are reset, but the display data are read in the data latch regardless of the condition of /dispoff. when the /dispoff function is canceled, the driver outputs non-select level (v 12 or v 43 ), then outputs the contents of the data latch at the next falling edge of the lp. at that time, if /dispoff removal time does not correspond to what is shown in ac characteristics, it cannot output the reading data correctly. ? table of truth-values is shown in "truth table" in functional operations. fr ac signal input pin for lcd drive waveform ? the input signal is level-shifted from logic voltage level to lcd drive voltage level, and controls the lcd drive circuit. ? normally it inputs a frame inversion signal. ? the lcd drive output pins' output voltage levels can be set using the line latch output signal and the fr signal. ? table of truth-values is shown in "truth table" in functional operations. md mode selection pin ? when set to v ss level "l", 4-bit parallel input mode is set. ? when set to v dd level "h", 8-bit parallel input mode is set. ? refer to "relationship between the display data and lcd drive output pins" in functional operations. s/c segment mode/common mode selection pin ? when set to v dd level "h", segment mode is set. elo 1 , eio 2 input/output pins for chip selection ? when l/r input is at v ss level "l", elo 1 is set for output, and eio 2 is set for input. ? when l/r input is at v dd level "h", elo 1 is set for input, and eio 2 is set for output. ? during output, set to "h" while lp ? xck is "h" and after 160 bits of data have been read, set
ST8016 ver 2.0 page 8/28 2008/05/07 to "l for one cycle (from falling edge to failing edge of xck), after which it returns to "h". ? during input, the chip is selected while el is set to "l" after the lp signal is input. the chip is non-selected after 160 bits of data have been read. option_vdd option selection pin ? for cog layout to reduce interface pins. ? normally let it open y 1 -y 160 lcd drive output pins ? corresponding directly to each bit of the data latch, one level (v 0 , v 12 or v 43 ) is selected and output. ? table of truth values is shown in "truth table" in functional operations. (common mode) symbol function v dd logic system power supply pin, connected to +2.5 to +5.5 v. v ss ground pin, connected to 0 v. v 0l , v 0r v 12l , v 12r v 43l , v 43r bias power supply pins for lcd drive voltage ? normally use the bias voltages set by a resistor divider. ? ensure that voltages are set such that v ss < v 43 < v 12 < v 0 . ? v il and v ir (i = 0,12, 43) must connect to an external power supply, and supply regular voltage that is assigned by specification for each power pin. elo 1 shift data input/output pin for bi-directional shift register ? output pin when l/r is at v ss level "l', input pin when l/r is at v dd level "h". ? when l/r = h, elo 1 is used as input pin, it will be pulled down. ? when l/r = l, elo 1 is used as output pin, it won't be pulled down. ? refer to "relationship between the display data and lcd drive output pins" in functional operations. eio 2 shift data input/output pin for bi-directional shift register ? input pin when l/r is at v ss level "l", output pin when l/r is at v dd level "h". ? when l/r = l, eio 2 is used as input pin, it will be pulled down. ? when l/r = h, eio 2 is used as output pin, it won't be pulled down. ? refer to "relationship between the display data and lcd drive output pins" in functional operations. lp shift clock pulse input pin for bi-directional shift register ? * data is shifted at the falling edge of the clock pulse. l/r input pin for selecting the shift direction of bi-directional shift register ? data is shifted from y 160 to y 1 when set to v ss level "l", and data is shifted from y 1 to y 160 when set to v dd level "h". ? refer to "relationship between the display data and lcd drive output pins" in functional operations. /dispoff control input pin for output of non-select level ? the input signal is level-shifted from logic voltage level to lcd drive voltage level, and controls the lcd drive circuit. ? when set to v ss level "l", the lcd drive output pins (y 1 -y 160 ) are set to level vss. ? when set to "l , the contents of the shift register are reset to not reading data. when the /dispoff function is canceled, the driver outputs non-select level (v 12 or v 43 ), and the shift data is read at the next falling edge of the lp. at that time, if /dispoff removal time does not correspond to what is shown in ac characteristics, the shift data is not read correctly. ? table of truth-values is shown in "truth table" in functional operations. fr ac signal input pin for lcd drive waveform ? the input signal is level-shifted from logic voltage level to lcd drive voltage level, and controls the lcd drive circuit. ? normally it inputs a frame inversion signal. ? the lcd drive output pins' output voltage levels can be set using the shift register output signal and the fr signal. ? table of truth-values is shown in "truth table" in functional operations. md mode selection pin ? when set to v ss level "l", single mode operation is selected; when set to v dd level "h" dual mode operation is selected. ? refer to "relationship between the display data and lcd drive output pins" in functional operations.
ST8016 ver 2.0 page 9/28 2008/05/07 di 7 dual mode data input pin ? according to the data shift direction of the data shift register, data can be input starting from the 81st bit. when the chip is used in dual mode, di 7 will be pulled down. when the chip is used in single mode, di 7 won't be pulled down(connect to v ss or v dd , avoiding floating.). ? refer to "relationship between the display data and lcd drive output pins" in functional operations. s/c segment mode/common mode selection pin ? when set to v ss level "l", common mode is set. di 6 -di 0 not used ? connect di 6 -di 0 to v ss or v dd , avoiding floating. xck not used ? xck is pulled down in common mode, so connect to v ss or open. option_vdd option selection pin ? for cog layout to reduce interface pin. y 1 -y 160 lcd drive output pins ? corresponding directly to each bit of the shift register, one level (v 0 , v 12 , v 43 , or v ss ) is selected and output. ? table of truth-values is shown in "truth table" in functional operations. 8.2 functional operations 8.2.1 truth table (segment mode) fr latch data /dispoff lcd drive output voltage level (y1-y160) l l h v 43 l h h v ss h l h v 12 h h h v 0 x x l v ss (common mode) fr latch data /dispoff lcd drive output voltage level (y1-y160) l l h v 43 l h h v 0 h l h v 12 h h h v ss x x l v ss notes: ? vss < v43 < v12 < v0 ? l : vss (0 v), h : vdd (+2.5 to +5.5 v), x : don't care ? "don't care" should be fixed to "h" or "l", avoiding floating. there are two kinds of power supply (logic level voltage and lcd drive voltage) for the lcd driver. supply regular voltage that is assigned by specification for each power pin.
ST8016 ver 2.0 page 10/28 2008/05/07 8.2.2 relationship between the display data and lcd drive output pins (segment mode) (a) 4-bit parallel input mode number of clocks md l/r eio 1 eio 2 data input 40 clock 39 clock 38 clock di 0 y 1 y 5 y 9 y 149 y 153 y 157 dl 1 y 2 y 6 y 10 y 150 y 154 y 158 di 2 y 3 y 7 y 11 y 151 y 155 y 159 l l output input di 3 y 4 y 8 y 12 y 152 y 156 y 160 di 0 y 160 y 156 y 152 y 12 y 8 y 4 dl 1 y 159 y 155 y 151 y 11 y 7 y 3 di 2 y 158 y 154 y 150 y 10 y 6 y 2 l h input output di 3 y 157 y 153 y 149 y 9 y 5 y 1 (b) 8-bit parallel input mode number of clocks md l/r eio 1 eio 2 data input 20 clock 19 clock 18 clock di 0 y 1 y 9 y 17 y 137 y 145 y 153 dl 1 y 2 y 10 y 18 y 138 y 146 y 154 di 2 y 3 y 11 y 19 y 139 y 147 y 155 di 3 y 4 y 12 y 20 y 140 y 148 y 156 di 4 y 5 y 13 y 21 y 141 y 149 y 157 di 5 y 6 y 14 y 22 y 142 y 150 y 158 di 6 y 7 y 15 y 23 y 143 y 151 y 159 h l output input di 7 y 8 y 16 y 24 y 144 y 152 y 160 di 0 y 160 y 152 y 144 y 24 y 16 y 8 dl 1 y 159 y 151 y 143 y 23 y 15 y 7 di 2 y 158 y 150 y 142 y 22 y 14 y 6 di 3 y 157 y 149 y 141 y 21 y 13 y 5 di 4 y 156 y 148 y 140 y 20 y 12 y 4 dl 5 y 155 y 147 y 139 y 19 y 11 y 3 di 6 y 154 y 146 y 138 y 18 y 10 y 2 h h input output di 7 y 153 y 145 y 137 y 17 y 9 y 1 (common mode) md l/r data transfer direction eio 1 eio 2 di 7 l y 160 y 1 output input x l (single) h y 1 y 160 input output x y 160 y 81 l y 80 y 1 output input input y 1 y 80 h (dual) h y 81 y 160 input output input notes: ? l : v ss (0 v), h : v dd (+2.5 to +5.5 v), x : don't care ? "don't care" should be fixed to "h" or "l", avoiding floating.
ST8016 ver 2.0 page 11/28 2008/05/07 8.2.3 connection examples of plural segment drivers (a) when l/r = l (b) when l/r = h y 160 y 160 y 160 y 1 y 1 y 1 eio2eio2eio2eio1eio1eio1 xck lp md fr di 7 -di 0 x c k l p m d f r d i 7 - d i 0 l/rl/rl/r v dd 8 top data last data data flow x c k l p m d f r d i 7 - d i 0 x c k l p m d f r d i 7 - d i 0 v ss y 160 y 160 y 160 y 1 y 1 y 1 eio2eio2eio2eio1eio1eio1 xck lp md fr di 7 -di 0 x c k l p m d f r d i 7 - d i 0 x c k l p m d f r d i 7 - d i 0 x c k l p m d f r d i 7 - d i 0 l/rl/rl/r v ss 8 top datalast data data flow
ST8016 ver 2.0 page 12/28 2008/05/07 8.2.4 timing chart of 4-device cascade connection of segment drivers n*n*n*n*n*1111122222 device adevice bdevice cdevice d top datalast data *n = 40 in 4-bit parallel input mode *n = 20 in 8-bit parallel input mode eo (device c) eo (device b) eo (device a) ei (device a) di7 - di0 xck lp fr
ST8016 ver 2.0 page 13/28 2008/05/07 8.2.5 connection examples for plural common drivers (a) single mode (l/r = l ) y 160 y 160 y 160 y 1 y 1 y 1 eio2eio2eio2eio1eio1eio1 lp v ss fr /dispoff l / r l p m d f r v ss (v dd ) first last flm / d i s p o f f l / r l p m d f r / d i s p o f f l / r l p m d f r / d i s p o f f d i 7 d i 7 d i 7 (b) single mode (l/r = h ) y 160 y 160 y 160 y 1 y 1 y 1 eio2eio2eio2eio1eio1eio1 fr l / r / d i s p o f f m d f r d i 7 lp /dispoff v ss (v dd ) first last l p v ss v dd flm l / r / d i s p o f f m d f r d i 7 l p l / r / d i s p o f f m d f r l p d i 7
ST8016 ver 2.0 page 14/28 2008/05/07 (c) dual mode (l/r = l ) y 160 y 160 y 160 y 1 y 1 y 1 eio2eio2eio2eio1eio1eio1 lp v ss fr /dispoff l / r l p m d f r v ss (v dd ) first last 2 flm1 / d i s p o f f l / r l p m d f r / d i s p o f f l / r l p m d f r / d i s p o f f first 2last 1 y 81 y 80 flm2 v dd d i 7 d i 7 d i 7 (d) dual mode (l/r = h ) y 160 y 160 y 160 y 1 y 1 y 1 eio2eio2eio2eio1eio1eio1 fr l / r / d i s p o f f m d f r d i 7 lp /dispoff first 1 last 2 l p v ss v dd flm1 l / r / d i s p o f f m d f r d i 7 l p l / r / d i s p o f f m d f r l p last 1first 2 y 80 y 81 flm2 v ss (v dd ) d i 7
ST8016 ver 2.0 page 15/28 2008/05/07 9 precautions precautions when connecting or disconnecting the power supply this ic has a high-voltage lcd driver, so a high current that may flow if voltage is supplied to the lcd drive power supply while the logic system power supply is floating may permanently damage it. the details are as follows, ? when connecting the power supply, connect the lcd drive power after connecting the logic system power. furthermore, when disconnecting the power, disconnect the logic system power after disconnecting the lcd drive power ? it is advisable to connect the serial resistor (50 to 100 ) or fuse to the lcd drive power v0 of the system as a current limiter. set up a suitable value of the resistor in consideration of the display grade. and when connecting the logic power supply, the logic condition of this ic inside is insecure. therefore connect the lcd drive power supply after resetting logic condition of this ic inside on /dispoff function. after that, cancel the /dispoff function after the lcd drive power supply has become stable. furthermore, when disconnecting the power, set the lcd drive output pins to level vss on /dispoff function. then disconnect the logic system power after disconnecting the lcd drive power. when connecting the power supply, follow the recommended sequence shown here. v dd v ss v dd v ss v dd v ss v dd /dispoff v 0
ST8016 ver 2.0 page 16/28 2008/05/07 10 absolute maximum ratings parameter symbol applicable pins rating unit note supply voltage (1) v dd v dd -0.3~ +7.0 v v 0 v 0l , v 0r -0.3 ~ +33.0 v v 12 v 12l , v 12r v 0 -10~ v 0 + 0.3 v supply voltage (2) v 43 v 43l , v 43r -0.3 ~ v ss + 10 v input voltage v i d1 7 -di 0 , xck, lp, l/r, fr, md, s/c, eio 1 , eio 2 , /dispoff, test 1 -0.3 to v dd + 0.3 v 1,2 storage temperature t stg -45 to +125 c notes: 1. ta = +25 c 2. the maximum applicable voltage on any pin with respect to v ss (0 v). 3. stress over the absolute max. ratings conditions will damaged the device permanently. 11 recommended operating conditions parameter symbol applicable pins min. typ. max. unit note supply voltage (1) v dd v dd +2.5 +5.5 v supply voltage (2) v 0 v 0l , v 0r +15.0 +30.0 v 1, 2 operating temperature t opr -25 +85 c notes: 1. the applicable voltage on any pin with respect to v ss (0 v). 2. ensure that voltages are set such that v ss < v 43 < v l2 < v 0 .
ST8016 ver 2.0 page 17/28 2008/05/07 12 electrical characteristics 12.1 dc characteristics (segment mode) (v ss = 0 v, v dd = +2.5 to +5.5 v, v 0 = + 15.0 to +30.0 v, t opr = -25 to +85 c) parameter symbol conditions applicable pins min. typ. max. unit note input "low" voltage v il 0.2v dd v input "high" voltage v ih di 7 -di 0 , xck, lp, l/r fr, md, s/c, eio 1 , eio 2 , /dispoff 0.8v dd v dd +0.7 v output "low" voltage v ol i ol = +0.4 ma +0.4 v output "high" voltage v oh i oh = -0.4 ma eio 1 , eio 2 v dd -0.4 v i lil v i = v ss -10 a input leakage current i lih v i = v dd di 7 -di 0 , xck, lp, lir, fr, md, s/c, eio 1 , eio 2 , /dispoff +10 a output resistance r on | ? v on | =0.5v v 0 = 30 v y 1 -y 160 1.0 1.5 k standby current i stb v ss 50 a 1 supply current (1) (non-selection) i dd1 v dd 2.0 ma 2 supply current (2) (selection) i dd2 v dd 7.0 ma 3 supply current (3) i 0 v 0l , v 0r 0.9 ma 4 notes: 1. v dd = +5.0 v, v 0 = +30.0 v, vi = v ss . 2. v dd = +5.0 v, v 0 = +30.0 v, f xck = 8 mhz, no-load, el = v dd . the input data is turned over by data taking clock (4-bit parallel input mode). 3. v dd = +5.0 v, v 0 = +30.0 v, f xck = 8 mhz, no-load, el = v ss . the input data is turned over by data taking clock (4-bit parallel input mode). 4. v dd = +5.0 v, v 0 = +30.0 v, f xck = 8mhz, f lp = 19.2 khz, f fr = 80 hz, no-load. the input data is turned over by data taking clock (4-bit parallel input mode). (common mode) (v ss = 0 v, v dd = +2.5 to +5.5 v, v 0 = + 15.0 to +30.0 v, t opr = -25 to +85 c) parameter symbol conditions applicable pins min. typ. max. unit note input "low" voltage v il 0.2v dd v input "high" voltage v ih di 7 -di 0 , xck, lp, l/ r fr, md, s/c, eio 1 , eio 2 , /dispoff 0.8v dd v dd +0.7 v output "low" voltage v ol i ol = +0.4 ma +0.4 v output "high" voltage v oh i oh = -0.4 ma eio 1 , eio 2 v dd -0.4 v i lil v i = v ss di 7 -di 0 , xck, lp, l/ r fr, md, s/c, eio 1 , eio 2 , /dispoff -10.0 a input leakage current i lih v i = v dd di 6 -di 0 , lp, l/r, fr, md, s/c, /dispoff +10.0 a input pull-down current i pd v i = v dd di 7 , xck, eio 1 , eio 2 100 a output resistance r on | ? v on | =0.5v v 0 = 30 v y 1 -y 160 1.0 1.5 k standby current i spd v ss 50 a 1 supply current (1) i dd v dd 80 a 2 supply current (2) i 0 v ol , v or 130 a 2 notes: 1. vdd = +5.0 v, v0 = +30.0 v, vi = vss 2. vdd = +5.0 v, v0 = +30.0 v, flp =19.2 khz, ffr = 80 hz, 1/240 duty operation, no-load.
ST8016 ver 2.0 page 18/28 2008/05/07 12.2 ac characteristics (segment mode 1) (v ss = 0 v, v dd = +2.5 to +3.0 v, v 0 = + 15.0 to +30.0 v, t opr = -25 10+85 c) parameter symbol conditions min. typ. max. unit note shift clock period t wck t r ,t f 10ns 125 ns 1 shift clock "h" pulse width t wckh 51 ns shift clock "l pulse width t wckl 51 ns data setup time t ds 30 ns data hold time t dh 40 ns latch pulse "h" pulse width t wlph 51 ns shift clock rise to latch pulse rise time t ld 0 ns shift clock fall to latch pulse fall time t sl 51 ns latch pulse rise to shift clock rise time t ls 51 ns latch pulse fall to shift clock fall time t lh 51 ns enable setup time t s 36 ns input signal rise time t r 50 ns 2 input signal fall time t f 50 ns 2 /dispoff removal time t sd 100 ns /dispoff "l" pulse width t wdl 1.2 s output delay time (1) t d cl = 15 pf 78 ns output delay time (2) t pd1 , t pd2 cl = 15 pf 1.2 s output delay time (3) t pd3 cl = 15 pf 1.2 s notes: 1. takes the cascade connection into consideration. 2. (t wck - t wckh - t wckl )/2 is maximum in the case of high speed operation. (segment mode 2) (v ss = 0 v, v dd = +3.0 to +4.5 v, v 0 = + 15.0 to +30.0 v, t opr = -25 10+85 c) parameter symbol conditions min. typ. max. unit note shift clock period t wck t r ,t f 10ns 82 ns 1 shift clock "h" pulse width t wckh 28 ns shift clock "l pulse width t wckl 28 ns data setup time t ds 20 ns data hold time t dh 23 ns latch pulse "h" pulse width t wlph 30 ns shift clock rise to latch pulse rise time t ld 0 ns shift clock fall to latch pulse fall time t sl 51 ns latch pulse rise to shift clock rise time t ls 30 ns latch pulse fall to shift clock fall time t lh 30 ns enable setup time t s 15 ns input signal rise time t r 50 ns 2 input signal fall time t f 50 ns 2 /dispoff removal time t sd 100 ns /dispoff "l" pulse width t wdl 1.2 s output delay time (1) t d cl = 15 pf 57 ns output delay time (2) t pd1 , t pd2 cl = 15 pf 1.2 s output delay time (3) t pd3 cl = 15 pf 1.2 s notes: 1. takes the cascade connection into consideration. 2. (t wck - t wckh - t wckl )/2 is maximum in the case of high speed operation.
ST8016 ver 2.0 page 19/28 2008/05/07 (segment mode 3) (v ss = 0 v, v dd = +5.0 0.5 v, v 0 = + 15.0 to +30.0 v, t opr = -25 to +85 c) parameter symbol conditions min. typ. max. unit note shift clock period t wck t r ,t f 10ns 50 ns 1 shift clock "h" pulse width t wckh 15 ns shift clock "l pulse width t wckl 15 ns data setup time t ds 10 ns data hold time t dh 12 ns latch pulse "h" pulse width t wlph 15 ns shift clock rise to latch pulse rise time t ld 0 ns shift clock fall to latch pulse fall time t sl 25 ns latch pulse rise to shift clock rise time t ls 25 ns latch pulse fall to shift clock fall time t lh 25 ns enable setup time t s 10 ns input signal rise time t r 50 ns 2 input signal fall time t f 50 ns 2 dispoff removal time t sd 100 ns dispoff "l" pulse width t wdl 1.2 s output delay time (1) t d cl = 15 pf 30 ns output delay time (2) t pd1 , t pd2 cl = 15 pf 400 ns output delay time (3) t pd3 cl = 15 pf 400 ns notes: 1. takes the cascade connection into consideration. 2. (t wck - t wckh - t wckl )/2 is maximum in the case of high speed operation. (common mode) (v ss = 0 v, v dd = +2.5 to +5.5 v, v 0 = + 15.0 to +30.0 v, t opr = -25 10+85 c) parameter symbol conditions min typ max unit shift clock period t wlp t r , t f 20ns 250 ns shift clock h pulse width t wlph v dd =5 0.5v v dd =2.5~4.5v 15 30 ns data setup time t su 30 ns data hold time t h 50 ns input signal rise time t r 50 ns input signal fall time t f 50 ns dispoff removal time t sd 100 ns dispoff l pulse width t wdl 1.2 us output delay time (1) t dl cl=10pf 200 ns output delay time (2) t pd1 ,t pd2 cl=10pf 1.2 us output delay time (3) t pd3 cl=10pf 1.2 us
ST8016 ver 2.0 page 20/28 2008/05/07 12.3 timing chart of segment mode fr lp /dispoff y 1 - y 160 t pd1 t pd3 t pd2 figure 12-1 timing characteristics (3) lp xck di7 - di0 /dispoff t wlph t ld t sl t lh t ls t wckh t f t r t wck t ds t dh top datalast data t wdl t sd t wckl t s 12 n* t d lp xck ei eo *n = 40 in 4-bit parallel input mode *n = 20 in 8-bit parallel input mode
ST8016 ver 2.0 page 21/28 2008/05/07 12.4 timing chart of common mode lp eio 2 eio 1 /dispoff t wdl t sd t dl t h t su t wlp t r t wlph t f fr lp y 1 - y 160 t pd1 t pd3 t pd2 /dispoff (common mode) (v ss = 0 v, v dd = +2.5 to +5.5 v, v 0 = + 15.0 to +30.0 v, t opr = -25 10+85 c) parameter symbol conditions min typ max unit shift clock period t wlp t r , t f 20ns 250 ns shift clock h pulse width t wlph v dd =5 0.5v v dd =2.5~4.5v 15 30 ns data setup time t su 30 ns data hold time t h 50 ns input signal rise time t r 50 ns input signal fall time t f 50 ns dispoff removal time t sd 100 ns dispoff l pulse width t wdl 1.2 us output delay time (1) t dl cl=10pf 200 ns output delay time (2) t pd1 ,t pd2 cl=10pf 1.2 us output delay time (3) t pd3 cl=10pf 1.2 us
ST8016 ver 2.0 page 22/28 2008/05/07 13 application circuit 13.1 application circuit for module 160 x 160 dot lcd panel fr lp /dispoff xck f r l p / d i s p o f f x c k eio 1 md s/c l/r eio 2 di 0 ~di 7 v ee v 4 v 3 v 2 v 1 v 0 v ss v dd 5 e i o 1 m d s / c l / r e i o 2 d i 0 ~ d i 7 flm lp /dispoff xck ac xd 0 ~xd 7 c o n t r o l l e r 50~100 ohm 5 8 8 y1~y160 y 1 ~y 160 ST8016 ST8016
ST8016 ver 2.0 page 23/28 2008/05/07 13.2 application circuit for cog layout (example) d u m m y d u m m y d u m m y d u m m y o p t i o n _ v d d y 1 6 0 1 9 8 d u m m y _ p a d v 0 199 l r 1 202 203 g n d v ss v d d 2 s / c 3 e i o 2 4 d i 0 5 6 7 8 d i 1 d i 2 d i 3 d i 4 9 10 11 12 d i 5 d i 6 d i 7 13 14 x c k d i s p o f f v 43 v 12 201 200 v ss 33 d u m m y _ p a d 3 7 y 0 ST8016 v 43 v 12 v 0 34 35 36 32 g n d g n d ST8016 l p 28 29 e i o 1 f r m d 313027 15 16 17 25 26
ST8016 ver 2.0 page 24/28 2008/05/07 14 pad diagram 1 32 v ss 33 202 203 x y chip size = 10030 15 um x 1070 15 um with scribe line subtrate connect to ground (0,0) ST8016 v ss ST8016 2 3 4 5 6 7 8 9 10 11 12 13 14 28 29 313027 v 43 v 12 v 0 201 200 199 v 43 v 12 v 0 34 35 36 88.9 40 (4826.3,172.9) (-4826.6,172.9) 89.7 40 unit: um pin# name x y pin# name x y 1 l/r -4 538.6 - 406.9 32 gnd 4720.4 - 404.3 2 vdd - 4227.0 - 409.7 33 vss 4904.5 - 344.1 3 s/c - 4074.5 - 406.9 34 v43 4904.5 - 125.7 4 eio2 - 3607.4 - 406.9 35 v12 4904.5 90.7 5 di0 - 3413.4 - 406.9 36 v0 4904.5 265.9 6 di1 - 3056.4 - 406.9 37 dummy_pad 4890.0 438.3 7 di2 - 2862.4 - 406.9 38 y1 4770.0 383.8 8 di3 - 2505.9 - 406.9 39 y2 4710.0 383.8 9 di4 - 2311.9 - 406.9 40 y3 4650.0 383.8 10 di5 - 1955.6 - 406.9 41 y4 4590.0 383.8 11 di6 - 1761.6 - 406.9 42 y5 4530.0 383.8 12 di7 -1 355.9 - 406.9 43 y6 4470.0 383.8 13 xck - 1161.9 - 406.9 44 y7 4410.0 383.8 14 dispoffb - 741.5 - 406.9 45 y8 4350.0 383.8 15 dummy_pad - 586.0 - 419.2 46 y9 4290.0 383.8 16 dummy_pad - 70.4 - 421.5 47 y10 4230.0 383.8 17 dummy_pad 152.5 - 398.3 48 y11 4170.0 383.8 18 dummy_pad 400.6 - 394.3 49 y12 4110.0 383.8 19 dummy_pad 768.3 - 398.7 50 y13 4050.0 383.8 20 dummy_pad 1183.9 - 398.7 51 y14 3990.0 383.8 21 dummy_pad 1474.6 - 395.3 52 y15 3930.0 383.8 22 dummy_pad 1595.8 - 411.9 53 y16 3870.0 383.8 23 dummy_pad 2092.5 - 412.6 54 y17 3810.0 383.8 24 dummy_pad 2318.2 - 404.5 55 y18 3750.0 383.8 25 option_vdd 2744.0 - 407.1 56 y19 3690.0 383.8 26 dummy_pad 3082.8 - 407.1 57 y20 3630.0 383.8 27 lp 3220.8 - 406.9 58 y21 3570.0 383.8 28 eio1 3701.6 - 406.9 59 y22 3510.0 383.8 29 fr 3895.6 - 406.9 60 y23 3450.0 383.8 30 md 4313.0 - 406.9 61 y24 3390.0 383.8 31 gnd 4525.0 -406.9 62 y25 3330.0 383.8
ST8016 ver 2.0 page 25/28 2008/05/07 63 y26 3270.0 383.8 113 y76 270.0 383.8 64 y27 3210.0 383.8 114 y77 210.0 383.8 65 y28 3150.0 383.8 115 y78 150.0 383.8 66 y29 3090.0 383.8 116 y79 90.0 383.8 67 y30 3030.0 383.8 117 y80 30.0 383.8 68 y31 2970.0 383.8 118 y81 - 30.0 383.8 69 y32 2910.0 383.8 119 y82 -90 .0 383.8 70 y33 2850.0 383.8 120 y83 - 150.0 383.8 71 y34 2790.0 383.8 121 y84 - 210.0 383.8 72 y35 2730.0 383.8 122 y85 - 270.0 383.8 73 y36 2670.0 383.8 123 y86 - 330.0 383.8 74 y37 2610.0 383.8 124 y87 - 390.0 383.8 75 y38 2550.0 383.8 125 y88 - 450.0 383.8 76 y39 2490.0 383.8 126 y89 - 510.0 383.8 77 y40 2430.0 383.8 127 y90 - 570.0 383.8 78 y41 2370.0 383.8 128 y91 - 630.0 383.8 79 y42 2310.0 383.8 129 y92 - 690.0 383.8 80 y43 2250.0 383.8 130 y93 - 750.0 38 3.8 81 y44 2190.0 383.8 131 y94 - 810.0 383.8 82 y45 2130.0 383.8 132 y95 - 870.0 383.8 83 y46 2070.0 383.8 133 y96 - 930.0 383.8 84 y47 2010.0 383.8 134 y97 - 990.0 383.8 85 y48 1950.0 383.8 135 y98 - 1050.0 383.8 86 y49 1890.0 383. 8 136 y99 - 1110.0 383.8 87 y50 1830.0 383.8 137 y100 - 1170.0 383.8 88 y51 1770.0 383.8 138 y101 - 1230.0 383.8 89 y52 1710.0 383.8 139 y102 - 1290.0 383.8 90 y53 1650.0 383.8 140 y103 - 1350.0 383.8 91 y54 1590.0 383.8 141 y104 -1410 .0 383.8 92 y55 1530.0 383.8 142 y105 - 1470.0 383.8 93 y56 1470.0 383.8 143 y106 - 1530.0 383.8 94 y57 1410.0 383.8 144 y107 - 1590.0 383.8 95 y58 1350.0 383.8 145 y108 - 1650.0 383.8 96 y59 1290.0 383.8 146 y109 - 1710.0 383.8 97 y60 1230.0 383.8 147 y110 - 1770.0 383.8 98 y61 1170.0 383.8 148 y111 - 1830.0 383.8 99 y62 1110.0 383.8 149 y112 - 1890.0 383.8 100 y63 1050.0 383.8 150 y113 - 1950.0 383.8 101 y64 990.0 383.8 151 y114 - 2010.0 383.8 102 y65 930.0 383. 8 152 y115 - 2070.0 383.8 103 y66 870.0 383.8 153 y116 - 2130.0 383.8 104 y67 810.0 383.8 154 y117 - 2190.0 383.8 105 y68 750.0 383.8 155 y118 - 2250.0 383.8 106 y69 690.0 383.8 156 y119 - 2310.0 383.8 107 y70 630.0 383.8 157 y120 -237 0.0 383.8 108 y71 570.0 383.8 158 y121 - 2430.0 383.8 109 y72 510.0 383.8 159 y122 - 2490.0 383.8 110 y73 450.0 383.8 160 y123 - 2550.0 383.8 111 y74 390.0 383.8 161 y124 - 2610.0 383.8 112 y75 330.0 383.8 162 y125 -2670.0 383.8
ST8016 ver 2.0 page 26/28 2008/05/07 163 y126 - 2730.0 383.8 184 y147 - 3990.0 383.8 164 y127 - 2790.0 383.8 185 y148 - 4050.0 383.8 165 y128 - 2850.0 383.8 186 y149 - 4110.0 383.8 166 y129 - 2910.0 383.8 187 y150 - 4170.0 383.8 167 y130 - 2970.0 383.8 188 y151 - 4230.0 383.8 168 y131 - 3030.0 383.8 189 y152 - 4290.0 383.8 169 y132 - 3090.0 383.8 190 y153 - 4350.0 383.8 170 y133 - 3150.0 383.8 191 y154 - 4410.0 383.8 171 y134 - 3210.0 383.8 192 y155 - 4470.0 383.8 172 y135 - 3270.0 383.8 193 y156 - 4530.0 383.8 173 y136 - 3330.0 383.8 194 y157 - 4590.0 383.8 174 y137 - 3390.0 383.8 195 y158 - 4650.0 383.8 175 y138 - 3450.0 383.8 196 y159 - 4710.0 383.8 176 y139 - 3510.0 383.8 197 y160 - 4770.0 383.8 177 y140 - 3570.0 383.8 198 dummy_pad - 4890.0 438.3 178 y141 - 3630.0 383.8 199 v0 - 4904.5 265.9 179 y142 - 3690.0 383.8 200 v12 - 4904.5 90.7 180 y143 - 3750.0 383.8 201 v43 - 4904.5 - 125.7 181 y144 - 3810.0 383.8 202 vss - 4904.5 - 344.1 182 y145 - 3870.0 383.8 203 gnd - 4781.8 - 404.9 183 y146 - 3930.0 383.8 14.1 gold bump size (unit: um) pad no. x y area (um 2 ) 38~197 45 72 3240 1~14,17,27~32,203 62 58 3596 33~36,199~202 58 62 3596 15,16,18,21~26 38 60 2280 19,20 60 38 2280 37,198 85 60 5100 wafer thickness = 675 20um, bump pad height (pad 1~198) = 18um, strength=30g
ST8016 ver 2.0 page 27/28 2008/05/07 15 applition note ( reference only ) 15.1 pcb and ito layout notice: pin name ito resistor values lgnd, gnd, v dd , vss less than 75 when v dd R 3.0v, and the smaller the better v0r, v0l less than 150 , and the smaller the better v12r, v12l, v34r, v12l less than 250 , and the smaller the better ps : above resistor value test on 3 lcd panel. 15.2 we suggest the ito resistor for lcd panel is less than 15 /square, and the resistor value is as smaller as better. 15.3 adjust v1 and v4 voltage to keep the v0-v1 = v4-vss relation to get better display quality. the (v0-v1)-(v4-vss) value had better less than 100mv. 15.4 add 0.1uf high frequency by-pass capacitor to filter the noise on v0~v4 to vss. 15.5 when op follower circuit is used, please be sure the op power is higher than v0 at least 1.5v. 15.6 eio1 and eio2 is enable pin for driver, please pay attention to the distance to avoid noise when cascade function is used. two chip connecting distance is as shorter as better.
ST8016 ver 2.0 page 28/28 2008/05/07 16 revision revision description page date page1, modify pin configuration 2000/05/16 application circuit 2000/07/25 pad allocation, bump size 2000/08/01 0.14 change pad name v5 as vss 2000/08/09 0.143 add pad 203 gold bump data 2000/08/17 0.152 add some bump information 2000/10/09 0.153 correct pad name 2000/11/02 0.16 update tcp(f18) information 2000/12/04 0.17 correct all v5 as vss 2000/12/19 0.2 ac/dc data revise 2000/12/26 0.23 correct segment mode md=l/h=4/8 bit (section 7.2.2) 2001/02/08 0.24 gold bump strength=30g 2001/03/01 0.30 dual mode describe correct and cog application circuit (section 12.2) 2001/05/22 0.31 correct some wrong word mistake 2001/06/11 0.32 add input/output circuit 2001/08/29 0.33 t sl min change to 51 , and change parameter name 2001/09/28 0.34 correct ac characteristics column 2001/10/04 0.35 change operating temperature from -20 c~85 c to -25 c~85 c 2002/06/07 1.2 modify v5 to vss in pad diagram table , and di 7 pin description for com mode 2005/01/31 1.3 modify ac characteristics 2005/09/23 1.4 add alignment mark 2005/10/19 1.5 add max value for input high voltage 2006/09/04 1.6 modify chip size and thickness with scribe line 2006/10/26 1.7 modify wafer thickness 25 2006/12/22 1.8 add pcb layout notice: resistance limitation between vdd and gnd 23 2007/2/6 1.9 modify all the data about absolute max voltage and recommend max voltage 2,16 2007/5/25 2.0 add application note 27 2008/05/07 the above information is the exclusive intellectual property of sitronix technology corp. and shall not be disclosed, distributed or reproduced without permission from sitronix.

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